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This shows you the differences between two versions of the page.
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pm:lab:lab0xc0-7 [2020/05/03 23:09] iuliana.brinzoi [Serial Memory 24c02] |
pm:lab:lab0xc0-7 [2020/05/04 20:26] (current) iuliana.brinzoi [I2C (Inter-Integrated Circuit)] |
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| After the master has generated the start condition, it sends to the data line (SDA) the address of the slave device with which it wants to communicate. The address is (most often) a 7-bit number (bits A6-A0 in the frame in the figure below). Bit 0 indicates whether the master initiates a Read operation (bit 0 is 1) or a Write operation (bit 0 is 0), as can be seen in the figure. | After the master has generated the start condition, it sends to the data line (SDA) the address of the slave device with which it wants to communicate. The address is (most often) a 7-bit number (bits A6-A0 in the frame in the figure below). Bit 0 indicates whether the master initiates a Read operation (bit 0 is 1) or a Write operation (bit 0 is 0), as can be seen in the figure. | ||
| - | {{: pm: lab: i2c1.png? 500 |}} | + | {{:pm:lab:i2c1.png?500|}} |
| The slave that recognizes its address sends an ACK to the master by setting the SDA line to LOW in the ninth clock cycle. The default state of SDA / SCL lines is HIGH due to pull-up resistors. The Master / Slave just "pulls" the lines on LOW. | The slave that recognizes its address sends an ACK to the master by setting the SDA line to LOW in the ninth clock cycle. The default state of SDA / SCL lines is HIGH due to pull-up resistors. The Master / Slave just "pulls" the lines on LOW. | ||
| Line 36: | Line 36: | ||
| === Stop Condition === | === Stop Condition === | ||
| After all data frames have been exchanged, the master generates the stop condition. This is done by releasing the SDA line (switching from LOW to HIGH) after releasing the SCL line (switching from LOW to HIGH). | After all data frames have been exchanged, the master generates the stop condition. This is done by releasing the SDA line (switching from LOW to HIGH) after releasing the SCL line (switching from LOW to HIGH). | ||
| + | |||
| + | {{:pm:lab:i2c14.png?500|}} | ||
| ===== I2C in Atmega324 ===== | ===== I2C in Atmega324 ===== | ||
| Line 45: | Line 47: | ||
| === TWSR - TWI Status Register (datasheet 21.9.3. - page 237) === | === TWSR - TWI Status Register (datasheet 21.9.3. - page 237) === | ||
| === TWDR - TWI Data Register (datasheet 21.9.4. - page 237) === | === TWDR - TWI Data Register (datasheet 21.9.4. - page 237) === | ||
| + | |||
| + | {{:pm:lab:i2c13.png?500|}} | ||
| ==== Library I2C Master - API ==== | ==== Library I2C Master - API ==== | ||
| Line 61: | Line 65: | ||
| {{: pm: lab: i2c7.png? 500 |}} | {{: pm: lab: i2c7.png? 500 |}} | ||
| - | ==== Serial Memory 24c02 ==== | + | ===== Serial Memory 24c02 ===== |
| Features: | Features: | ||
| * Capacity: 2048 bits = 256 bytes | * Capacity: 2048 bits = 256 bytes | ||
| Line 74: | Line 78: | ||
| In order to write to memory, a sequence must be sent: | In order to write to memory, a sequence must be sent: | ||
| + | |||
| START | START | ||
| * Send header + slave address + transmission bit | * Send header + slave address + transmission bit | ||
| Line 83: | Line 88: | ||
| In order to read from memory, the following sequence must be sent: | In order to read from memory, the following sequence must be sent: | ||
| + | |||
| START | START | ||
| * Send header + slave address + transmission bit | * Send header + slave address + transmission bit | ||
| Line 96: | Line 102: | ||
| {{:pm:lab:i2c9.png?500|}} | {{:pm:lab:i2c9.png?500|}} | ||
| - | ==== Setup ==== | + | ===== Setup ===== |
| - | {{: pm: lab: i2c11.png? 500 |}} | + | {{:pm:lab:i2c11.png?500|}} |
| - | After executing all tasks- : | + | After executing all tasks: |
| - | {{: pm: lab: i2c8.png? 500 |}} | + | {{:pm:lab:i2c8.png?500|}} |
| - | {{: pm: lab: i2c12.png? 500 |}} | + | {{:pm:lab:i2c12.png?500|}} |
| - | ==== Tasks ==== | + | ===== Tasks ===== |
| The skeleton of the program is here: {{: pm : lab: lab_0xc6_skeleton.zip |}}. | The skeleton of the program is here: {{: pm : lab: lab_0xc6_skeleton.zip |}}. | ||
| + | |||
| + | <hidden> | ||
| + | Solution: {{:pm:lab:arhiva.zip|}} | ||
| + | </hidden> | ||
| 2kbits serial memory - {{: pm: lab: n24c02-d.pdf |}} | 2kbits serial memory - {{: pm: lab: n24c02-d.pdf |}} | ||
| - In the first task a simple sequence must be sent to obtain the acknowledgment from the slave device with the slave address 0. | - In the first task a simple sequence must be sent to obtain the acknowledgment from the slave device with the slave address 0. | ||
| - | - Using the method from the previous task, to scan and thus to detect which devices exist on the I2C bus | + | - Use the method from the previous task to scan and thus to detect which devices exist on the I2C bus. |
| - In this task it must be written in the serial memory that has the slave address 0. The writing will be done at memory address 0 and memory address 1. | - In this task it must be written in the serial memory that has the slave address 0. The writing will be done at memory address 0 and memory address 1. | ||
| - | - In this task the memory content (first 4 bytes) of the slave at address 0 must be read | + | - In this task the memory content (first 4 bytes) of the slave at address 0 must be read. |
| Responsible: Adrian Mocanu | Responsible: Adrian Mocanu | ||
