This lab covers the topic of I2C. For more in-depth knowledge about working with I2C you can consult the ATmega324 datasheet.

The I2C (or IIC - Inter-Integrated Circuit) protocol is a synchronous, multi-master - multi-slave serial communication protocol, developed by Phillips in 1982. An I2C bus consists of the following signals:

• SDA - data line
• SCL - clock signal

The clock signal is generated by the master and the data line is controlled by both the master and the slave. Only one device can control the data line at a time. Because of this, the I2C protocol is half-duplex.

Compared to the SPI where the master activates, via the Slave Select signal, the device with which he wanted to communicate, I2C does not require such an additional signal. The I2C protocol introduces the notion of Slave Address. The address of a slave device is a 7-bit (most common), 8-bit, or 10-bit number. Communication between a master and a slave is done through messages and is always initiated by the master. These messages can be broken into two types of frames:

• an address frame
• one or more data frames

These frames are exchanged only after the master has sent the start condition. The end of a message is identified by the stop condition.

Before the master sends to the data line the address of the slave with which it wants to communicate, it must generate a start condition. The start condition causes all slave devices to “listen” to the data line because an address will follow. To generate this condition, the master leaves the SCL line in HIGH and sets the SDA line to LOW.

After the master has generated the start condition, it sends to the data line (SDA) the address of the slave device with which it wants to communicate. The address is (most often) a 7-bit number (bits A6-A0 in the frame in the figure below). Bit 0 indicates whether the master initiates a Read operation (bit 0 is 1) or a Write operation (bit 0 is 0), as can be seen in the figure.

The slave that recognizes its address sends an ACK to the master by setting the SDA line to LOW in the ninth clock cycle. The default state of SDA / SCL lines is HIGH due to pull-up resistors. The Master / Slave just “pulls” the lines on LOW.

The master identifies whether it received ACK (SDA set to LOW) or NACK (SDA remained HIGH during the ninth clock cycle).

If the master has received the ACK (if there is a slave on the bus with the respective address), it can continue with the data transmission (write operation), or with the data reception (read operation). The number of data frames is arbitrary, they can be exchanged as many times. Each frame sent / received is ACK'd or NACK'd. Depending on the operation (read or write), the ACK / NACK is sent by either the master or the slave.

• If the master has initiated a write operation, each frame sent is confirmed (ACK'd) by the slave
• If the master has initiated a read operation, each frame received is confirmed by (ACK'd) the master . When the master wants to stop the transaction after a certain number of frames has been received, instead of sending ACK sends NACK. Thus the slave will stop transmitting

After all data frames have been exchanged, the master generates the stop condition. This is done by releasing the SDA line (switching from LOW to HIGH) after releasing the SCL line (switching from LOW to HIGH).

Atmega324p can work in both I2C Master and I2C Slave mode. It is also known as TWI (Two-Wire Interface).

In this lab we will use a library to make working with I2C devices easier. Its API can be seen in the “i2c_master.h” header in the lab framework.

Features:

• Capacity: 2048 bits = 256 bytes
• Storage technology: EEPROM
• Connection interface: I2C
• Maximum number of slaves on the same bus: 8
• I2C header: 0xA
• Number of bytes of memory address: 1
• Type of wait after writing: 4 msec

The header, the first byte that is always sent after Start, is a byte composed of the header + the slave address + a bit that indicates whether a transmission (0) (write) or a reception follows (1) (read).

In order to write to memory, a sequence must be sent:

START

• Send header + slave address + transmission bit
• Send memory address
• Send the data byte

STOP

In order to read from memory, the following sequence must be sent:

START

• Send header + slave address + transmission bit
• Send memory address

START

• Send header + slave address + reception bit
• Receive data and send ACK
• …
• Receive data and send ACK
• Receive data and send NO_ACK

STOP

After executing all tasks:

The skeleton of the program is here: lab_0xc6_skeleton.zip.

2kbits serial memory - n24c02-d.pdf

1. In the first task a simple sequence must be sent to obtain the acknowledgment from the slave device with the slave address 0.
2. Use the method from the previous task to scan and thus to detect which devices exist on the I2C bus.
3. In this task it must be written in the serial memory that has the slave address 0. The writing will be done at memory address 0 and memory address 1.
4. In this task the memory content (first 4 bytes) of the slave at address 0 must be read.

Responsible: Adrian Mocanu