This lab covers the topic of SPI. For more in-depth knowledge about working with SPI you can consult the ATmega324 datasheet and Serial Peripheral Interface.

SPI is a synchronous standard developed by Motorola operating in full-duplex mode (data transfer takes place in both directions simultaneously). Devices communicate using a master-slave architecture (only one master is allowed, one or multiple slaves can be connected using SP where I),the master is initiating the communication. SPI is also called the “four wire” serial bus. The four signals used are the following:

• MOSI — Master Output Slave Input (output from master to slave input)
• MISO — Master Input Slave Output (output from slave to master input)
• SCK — Serial Clock
• CS/SS — Chip Select/Slave Select (active LOW; output from master to slave)

We can see that there are two signals used for data transmission: MOSI and MISO. Data transmission on SPI is done synchronously using the clock signal SCK. The CS/SS signal is used to select the slave device on the bus that is currently addressed.

Multiple slave devices can be connected to a single master, selecting a particular slave with the CS/SS signal associated with the slave. The other three signals are shared.

In a daisy chain topology data is transferred from one device to the next and in the end the last device and from the last device data is transferred back to the master. So the first byte transferred, in the end it reaches the last SPI slave device in the daisy chain topology. Data from the first slave reaches the master lastly.

To start the communication with the master device should set the clock to a frequency at most equal to the frequency supported by the slave (usually up to a few MHz). The master then selects the desired slave device, putting 0 on the SS line. During a SPI cycle, the transmission is full-duplex:

• the master sends a bit on the MOSI line, and the slave reads it
• the slave sends a bit on the MISO line, and the master reads it

The SPI communication usually involves the existence of two shift registers (one in the master and one in the slaves, circularly connected).

Usually the first bit shifted on the MISO / MOSI lines is the most significant bit, while a new bit is added to the least significant position in the register. After the entire word was sent, through shifting, the master and slave exchanged the values in the two shift registers. If there is data to be transmitted, the process starts again. When there is no data to be transmitted, the master interrupts the clock generation and places 1 on the SS line associated with the slave. The slave devices that were not selected by their associated SS signal will ignore the signals on the SCK and MOSI and will not generate anything on the MISO. The master can select only one slave at a time.

Clock Polarity (CPOL) configures the IDLE state of the clock. As we can see, for CPOL=0, the clock is idle LOW, and for CPOL=1 the clock signal is idle on HIGH.

Clock phase (CPHA) configures when the data is generated on the output and when the data is read. On one of the clock edges (leading or trailing) data is generated, and on the next one the data is sampled.

Leading edge is the first edge of the clock cycle. For a clock that goes from LOW to HIGH and back to LOW, the leading edge is the rising edge (LOW to HIGH).

For CPHA=0 data is generated before the leading edge (first edge of the clock), and is sampled on the leading edge (rising for CPOL=0 and falling for CPOL=1).

For CPHA=0 data is generated on the leading edge (first edge of the clock), and is sampled on the trailing edge (falling for CPOL=0 and rising for CPOL=1).

The SPI included in the atmega324 microcontroller can operate as both master and slave.

Bit 6 - SPE - SPI Enable - write this bit to 1 to enable SPI.

Bit 5 - DORD - Data Order - writing this bit to 1, the LSB of the data word is transmitted first, otherwise, the MSB of the data word is transmitted first.

Bit 4 - MSTR - Master/Slave Select - when this bit is 1 the interface works in master mode, otherwise works in slave mode.

Bit 3 – CPOL - Clock Polarity - when this bit is written to 1, SCK is high when idle, otherwise SCK is low when idle.

Bit 2 – CPHA - Clock Phase - the settings of this bit determine if data is sampled on the leading (first) or trailing (last) edge of SCK.

Bits 1:0 – SPR1, SPR0 - SPI Clock Rate - these two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave.

Bit 7 – SPIF - SPI Interrupt Flag - is set to 1 when a transmission has finished.

Bit 0 – SPI2X - Double SPI Speed Bit - when this bit is set to 1 the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode. This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower.

A read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.

Initialize the SPI as a Master.

/* enable SPI  */
SPCR0 |= (1 << SPE0);
	
/* set master mode */
SPCR0 |= (1 << MSTR0);
	
/* set prescaler 16 */
SPCR0 |=  (1 << SPR00);

Perform a simple transmission.

/* Start transmission */
SPDR0 = data;

/* Wait for transmission complete */c
while(!(SPSR0 & (1 << SPIF0)));

Perform a simple reception.

/* Wait for reception complete */
while(!(SPSR0 & (1 << SPIF0)));
	
/* Return Data Register */
return SPDR0;

Sketch is available here: lab5.zip

• Output Shift Register - 74HC595 - Datasheet
• Input Shift Register - 74HC597 - Datasheet

1. To the PB0 pin there is connected an output shift register. The connection between the microcontroller and the shift register is established using SPI Bus topology. Initialize the SPI Protocol and display the message “SALAH” on the 7-segment display. Follow the comments marked with TODO 1 in the code skeleton.
2. To the PB1 pin there is connected an input shift register. The connection between the microcontroller and the shift register is established using SPI Bus topology. Read the status of the buttons and turn on the LEDs associated with the pressed buttons. Follow the comments marked with TODO 2 in the code skeleton.
3. SPI is a full-duplex protocol. Read the state of the buttons, turn on the LEDs associated with the pressed buttons and display the letter on the 7-segment display. Take the letter from the digits_pattern array based on the value resulted from pressing the buttons. Follow the comments marked with TODO 3 in the code skeleton.

Responsabil: Alice Suiu