This lab covers the topic of ADC. For more in-depth knowledge about working with ADC you can consult the ATmega324 datasheet (Datasheet ATmega324).

An analog-to-digital converter (ADC) is a system that converts an analog signal into a digital signal. Similarly, the digital-to-analog converter (DAC) performs the reverse function. In order to perform the conversion, the ADC samples periodically the input signal obtaining an approximation of the discrete values of the signal. This process can lead to some errors/noise proportional to the sampling rate and resolution.

The resolution represents the number of discrete values that can be produced over the range of analog values in a measurement period. The discrete values are usually in binary form, so a common way to represent resolution is in audio bit depth (the number of bits of information in each sample). For example, for a resolution of 8 bits, we can encode the analog input signal in 256 different levels, the values ranging from 0 to 255. Resolution can also be expressed in volts, each level representing a fraction of the voltage measurement range. For example, for a range of 0- 5V and an 8-bit resolution, the subdivision would be (5V – 0V) / (2 ^ 8).

The sampling rate represents the time at which the values of the analog input signal are read. The time is divided into discrete intervals, each sampling a value from the input signal. The Nyquist frequency tells us that it is mandatory for the sampling rate to be at least twice the frequency of the analog input signal so that the signal can be reconstructed afterwards. There appears a problem where frequencies above half the Nyquist frequency are sampled because they are incorrectly detected as lower frequencies. This process is called aliasing.

Has a bank of comparators sampling the input signal in parallel, each firing for their decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range.

Uses a comparator to successively narrow a range that contains the input voltage. At each successive step, the converter compares the input voltage to the output of an internal digital to analog converter which might represent the midpoint of a selected voltage range. At each step in this process, the approximation is stored in a successive approximation register (SAR). Successive approximation ADC`s are cheaper than direct conversion ADC`s, and have a smaller footprint on the IC, but they are also slower.

Is a newer design that offers low conversion noise and good resolution. Sigma-delta convertors are appropriate for application that require high resolution, but not the fastest conversion. As stated above, an ADC conversion is not instant, it requires a certain amount of time to complete. This raises a issue: what will happen with the result of the conversion if the input signal will change during this conversion time. The conversion result might not correspond then to the real value of the signal. To solve this, an internal input buffer is used. When the input signal is sampled, switch S1 is closed, S2 open, so that the Csh capacitor will hold a voltage equal to the input signal. S1 will then open, S2 will close and the conversion will begin. The two switches will hold this state until the conversion will end. Capacitor Csh will hold the (analog) value of the signal while the during the A/D conversion.

The ADC included in the atmega324 microcontroller is a 10-bit successive approximation ADC. It is connected to an 8-pin channel, the inputs being multiplexed from Port A. The maximum resolution is 10 bits and it can measure voltage from 0-5V range. It can also amplify the input signal if it has a small amplitude in steps of 0 dB (1x), 20 dB (10x) or 46 dB (200x). The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. The result is right adjusted but it can optionally be set left adjusted by setting the ADLAR bit in ADMUX. If the result is right adjusted, the order to read the ADC value is ADCL and ADCH, otherwise is reversed. This must be done to ensure that the data read belong to the same conversion. After the last register is read, access to Data Registers is blocked until the next conversion. The ADC has also its own interrupt that can be triggered when a conversion completes. For a single ended conversion, the result is ADC = Vin * 1024 / Vref.

To check if a ADC conversion is completed, the ADIF bit from the ADCSRA register can be tested, or an interrupt can be generated by setting the ADIE bit in the ADCSRA register.

Bit 7:6 - REFS1:0 Reference Selection Bits → this bits select the voltage reference for ADC Bit 5 - ADLAR ADC Left Adjust Result → write 1 to ADLAR to left-adjust the result

BIT 4:0 - MUX 4:0 Analog Channel Gain Selection Bits → this bits select what combination of input pins is connected to the ADC

Bit 7 - ADEN ADC Enable → writing this bit to ena enables the ADC

Bit 6 - ADSC ADC Start Conversion → write this bit to one to start each conversion; in free running mode write this bit to one to start the first conversion

Bit 5 - ADATE ADC Auto Trigger Enable → the ADC will start a conversion on a positive edge of the selected trigger signal

Bit 4 - ADIF ADC Interrupt Flag → This bit is set when an ADC conversion completes and the Data Registers are updated

Bit 3 - ADIE ADC Interrupt Enable → when this bit is written to one and the global interrupts are enabled, the ADC Conversion Complete Interrupt is activated

Bit 2:0 - ADPS2:0 ADC Prescaler Select Bits

When ADC conversion is complete, the result is found in these two registers.

Bit 7,5:3 - Reserved

Bit 2:0 - ADTS 2:0 ADC Auto Trigger Source → if ADATE in ACSRA is set, the value of these bits selects which source will trigger an ADC conversion; otherwise it will have no effect

If bit ADATE in ADCSRA register is not set, bits ADPS2:0 will have no effect and ADC will work in Single Conversion Mode. In this mode, a single conversion is triggered by writing ADSC bit in ADCSRA register. Bit ADSC will be cleared by hardware when the conversion ends.

If bit ADATE in ADCSRA register is set, ADC is set to AutoTrigger mode and bits ADPS2:0 control the trigger source. In Free Running mode, write bit ADSC in ADCSRA register to start the first conversion. ADC will then start a new conversion as soon as the current conversion is done. The result will be overwritten, bit ADSC will not be cleared.

In Analog Comparator mode, ADC can compare two analog signals and trigger an interrupt. For more details, see chaper 22. Analog Comparator in datasheet.

If bits ADTS2:0 are set to External Interrupt Request, a rising edge on an input pin can trigger an ADC conversion.

Timers can be used for a precise control of ADC`s sampling rate. Using ADTS2:0 bits, a timer event (compare match, overflow) can be used to start a new conversion.

When the conversion is done, the ADC module can generate a new interrupt that can be used to control the timing of the next timer event.

Init ADC to read from PA1 pin (channel 1).

ADMUX = 0;
/* ADC1 - channel 1 */
ADMUX |= (1 << MUX0);
/* AVCC with external capacitor at AREF pin */
ADMUX |= (1 << REFS0);

ADCSRA = 0;
/* set prescaler at 128 */
ADCSRA |= (7 << ADPS0);
/* enable ADC */
ADCSRA |= (1 << ADEN);

Read the ADC value.

/* start conversion */
ADCSRA |= (1 << ADSC);
/* wait until conversion is complete */
while (!(ADCSRA & (1 << ADIF)));
uint32_t result = ADC;

Sketch is available here: lab3.zip

1. To the PA1 pin there is connected a voltage divider. Push buttons control the output voltage. Read the value from the pin using polling and print the corresponding voltage to the serial console.
2. There is a temperature sensor (LM35) connected to PA0 pin. Configure the ADC to read the value from the sensor using interrupts. Display on the UART console the voltage and the temperature in Celsius degrees associated with it.
3. Configure the ADC to start a conversion every 10 ms using Timer 0 compare match as trigger event and read the value from the potentiometer connected to PA6 using interrupts.

Responsabil: Iuliana Brinzoi