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2025/08/16 00:24
Laboratorul 02. Intro to IPv6
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eduard.dumistracel
2025/08/16 00:23
Laboratorul 01. Setup Infrastructure
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Informații
Reguli generale și notare
Cursuri
Cursul 0 - Legea lui Moore
Cursul 1 - De la porți logice la procesoare
Cursul 2 - Introducere în Verilog
Cursul 3 - Sumatoare
Cursul 4 - Calculatorul SAP-1 (1)
Cursul 5 - Calculatorul SAP-1 (2)
Cursul 6 - Reprezentarea numerelor
Cursul 7 - Implementarea unei mașini de calcul
Cursul 8 - Măsurarea performanței
Cursul 9 - De la CISC la RISC
Cursul 10 - Banda de asamblare
Cursul 11 - Banda de asamblare (2)
Cursul 12 - Întreruperi
Cursul 13 - Cache
Laboratoare
00 - Introducere în logica digitală
01 - Introducere în Verilog
02 - Tipuri de descriere a modulelor în Verilog
03 - FPGA & Debugging
04 - Automate cu stări
05 - Afișajul cu 7 segmente
06 - Sumatoare
07 - Sumatorul CLA
08 - Proiectul SOC-1
09 - Proiectul SOC-1 - Continuare
10 - Pipeline
Resurse
Breviar teoretic
Blocking vs Nonblocking
Tutoriale
Vivado
Instalare Vivado 2017.4
Creare proiect Vivado
Simulare proiect Vivado
Programare FPGA Vivado
soc.txt · Last modified: 2024/02/29 14:29 (external edit)
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