• Deadline: 22.12.2023, 23:59
• Publish date: 11.12.2022
• Last update: 11.12.2022, 00:00
• History:
  • 11.12.2022, 00:00
    • Publish the assignment

This assignment exercise the basic notions of Verilog by implementing complex sequential circuits. You will:

• Understand numeral representations by implement an arithmetic algorithm for processing integer numbers
• Divide and conquer - implement a finite state machine, based on a given scheme;
• Interact with memory elements (register) when you process the data;

In order to implement the requirements, you shall build a finite state machine to divide the operations executed per clock cycle. This automata communicates with additional modules with determined behavior. The detailed implementation for each module is described below.

Finite state machine implementation, this module also acts as a top module for the design (the one that have all the additional modules instantiated in it).

This module respects the following interface:

module floating_point_fsm(
        input         clk,
        input         rst,
        input         en,
        input [11:0]  a,
        input [11:0]  b,
        output reg    done,
        output [11:0] out
    );                

The signals' description for this module is:

• clk - clock signal;
• rst - reset signal - used to bring the module back to it's initial state;
• en - when this signal asserts, it marks the valid information for a and b in the next clock cycle;
• a - value for the first operand, expressed in sign_exponent_mantissa;
• b - value for the second operand, expressed in sign_exponent_mantissa;
• done - 1 when the result is ready;
• out - the result of the multiplication;

The module functionality is:

• Storing the input values a and b in their corresponding registers after the en signal gets asserted.
• Executing the operation and putting it on the output out; when out is available, done shall be one, to signalize that the out is available for the outside modules to be used.

We already have the input (A and B) and output (RES) registers instantiated inside and also an auxiliary register for saving the multiplication result (MUL) with their control signals for writing and reading and the proper connections with the environment, except the ones with the booth_mul.

This module actively used the booth_mul module to perform any multiplication operations needed.

• For the floating point implementation, the behavior of the register is the one studied in the lab.
• You can modify the state machine as you like, as long as it respects the requirements.

• In the project resources recourses there are already the files that you need and the prerequisite modules.
• The project archive that you shall upload (zip compression type) must include in it's root only:
  • the floating_point_fsm.v and the booth_mul.v files (you can already find them in the project skeleton);
  • other user-defined files (*.v), if used in your choice of implementation;
  • a README file, which shall contain at least:
    • your name and group;
    • general presentation of your solution;
    • description of any complex coding parts that you consider additional explanation is needed and they are too long to be an inline comment;
• The archive shall not contain any other files from the implementation folder (i.e. test files, project specific files, etc).

• +10.0 pts.: Correct implementation with the tests passing
  • 6.0 pts.: Multiplication Module
  • 4.0 pts.: IEEE754 Multiplication
• -10.0 pts.: using looping instructions with variable steps (i.e. while x > 0);
• -6.0 pts.: using * operator;
• -1.0 pts.: the absence of the README file;
• -1.0 pts.: bad coding style (chaotic indentation, irregular spacing, strange naming for variables, etc.);
• -0.5 pts.: incorrect using of continuous assignments ( assign ), procedural blocking ( = ) and non-blocking ( ⇐ ) assignments;
• -0.2 pts.: other generic implementation issues (/issue);
• -0.1 pts.: useless code comments.

Remember that you have an error counter already implemented in each testcase inside the project files, which tells you exactly when an error is detected. However, do not count on that; the project evaluation is done manually, after analyzing the code and the anti-plagiarism report.

Even if you do not finish the assignment, you can receive up to 25% of the grade if you properly explain your idea in the README file. Your code must pass the compilation and run.

• VIVADO Project Files - skel_vivado
• XILINX Project Files - skel_xilinx
• IEEE754 Multiplication Article -

• Multiplication algorithms - wiki