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ac-is:teme-ie:proiect [2023/12/13 19:09] ionut.pascal [Grading] |
ac-is:teme-ie:proiect [2024/01/07 18:47] (current) ionut.pascal old revision restored (2023/12/13 23:58) |
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| * Hard Deadline: **28.12.2023**, **23:59** | * Hard Deadline: **28.12.2023**, **23:59** | ||
| * Publish date: **13.12.2023** | * Publish date: **13.12.2023** | ||
| - | * Last update: **13.12.2023, 22:00** | + | * Last update: **13.12.2023, 23:50** |
| * History: | * History: | ||
| - | * 13.12.2023, 22:00 | + | * 13.12.2023, 23:50 |
| * Publish the assignment | * Publish the assignment | ||
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| ===== Description and requirements ===== | ===== Description and requirements ===== | ||
| + | Floating point has a long history in the engineering field and in computer science. The promoter was Leonardo Torres Quevedo back in 1914; nowadays, we use IEEE754 Standard Implementation. [[https://en.wikipedia.org/wiki/Floating-point_arithmetic|Wiki]] | ||
| + | The assignment consists in implementing a floating point multiplication algorithm for 2 numbers with the following format (S_EEEE_MMMMMMM): | ||
| + | * 1 sign bit - S | ||
| + | * 4 exponent bits - E | ||
| + | * 7 mantissa bits - M | ||
| + | The implementation can follow the proposed state machine: | ||
| + | {{ :ac-is:teme-ie:untitled_diagram.jpg?nolink |}} | ||
| + | Because we encounter a multiplication of fixed point (mantissa), we should implement a dedicated module responsible for this operation. The Booth algorithm is a suitable option which reduces the complexity but keeps a good understanding behind. The size of the operands is dependent on the size of the mantissa. | ||
| + | |||
| + | Requirements: | ||
| + | - Implement Booth algorithm in the dedicated file for 2 8bit operands: | ||
| + | - Take 2 random 8bit numbers of your choice and demonstrate the algorithm on the paper; | ||
| + | - Implement the Verilog code. | ||
| + | - Implement the floating point multiplication algorithm: | ||
| + | - Take 2 random 12bit numbers of your choice which respects the floating point format and demonstrate the multiplication on the paper; | ||
| + | - Implement the Verilog code. | ||
| + | |||
| + | <note important>Don't forget to follow the TODO's inside the code and check for the errors and messages in the console! Checking is implemented inside the testcase!</note> | ||
| + | |||
| ===== Implementation ===== | ===== Implementation ===== | ||
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| ===== Notes ===== | ===== Notes ===== | ||
| - | * For the floating point implementation, the behavior of the register is the one studied in the lab. | + | * For the floating point implementation, the behavior of the register is the one studied in the [[ac-is:lab-ie:lab02#The Register|lab]]. |
| * You can modify the state machine as you like, as long as it respects the requirements. | * You can modify the state machine as you like, as long as it respects the requirements. | ||
| + | * For VIVADO, the top module for simulation is the booth test; when implementing the floating point multiplication, don't forget to change the test | ||
| Line 95: | Line 115: | ||
| * general presentation of your solution; | * general presentation of your solution; | ||
| * description of any complex coding parts that you consider additional explanation is needed and they are too long to be an inline comment; | * description of any complex coding parts that you consider additional explanation is needed and they are too long to be an inline comment; | ||
| + | * Pictures/Scans of your paper demonstrations. | ||
| * The archive shall __**not**__ contain any other files from the implementation folder (i.e. test files, project specific files, etc). | * The archive shall __**not**__ contain any other files from the implementation folder (i.e. test files, project specific files, etc). | ||
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| * +10.0 pts.: Correct implementation with the tests passing | * +10.0 pts.: Correct implementation with the tests passing | ||
| - | * 6.0 pts.: Multiplication Module | + | * 0.5 pts.: Booth Multiplication Example - 2 8bit numbers on your choice |
| - | * 4.0 pts.: IEEE754 Multiplication | + | * 5.5 pts.: Multiplication Module |
| + | * 0.5 pts.: Floating Point Multiplication Example - 2 12bit numbers with the specified format of your choice | ||
| + | * 3.5 pts.: Floating Point Multiplication | ||
| + | * 0.5 pts.: (bonus) Add your numbers in the test file; verify there is a match. | ||
| * -10.0 pts.: using looping instructions with variable steps (i.e. while x > 0); | * -10.0 pts.: using looping instructions with variable steps (i.e. while x > 0); | ||
| * -6.0 pts.: using * operator in the booth_mul implementation; | * -6.0 pts.: using * operator in the booth_mul implementation; | ||
| - | * -2.0 pts.: not using the ''booth_mul'' module for implementing the FSM | + | * -1.0 pts.: not using the ''booth_mul'' module for implementing the FSM |
| * -1.0 pts.: the absence of the README file; | * -1.0 pts.: the absence of the README file; | ||
| * -1.0 pts.: bad coding style (chaotic indentation, irregular spacing, strange naming for variables, etc.); | * -1.0 pts.: bad coding style (chaotic indentation, irregular spacing, strange naming for variables, etc.); | ||
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| ===== Recourses ===== | ===== Recourses ===== | ||
| - | * **VIVADO Project Files** - {{:ac-is:teme-ie:proiect:lab_project_vivado.zip| skel_vivado}} | + | * **VIVADO Project Files** - {{:ac-is:teme-ie:lab_project_vivado.zip| skel_vivado}} |
| - | * **XILINX Project Files** - {{:ac-is:teme-ie:proiect:lab_project_xilinx.zip| skel_xilinx}} | + | * **XILINX Project Files** - {{:ac-is:teme-ie:lab_project_xilinx.zip| skel_xilinx}} |
| - | * **IEEE754 Multiplication Article** - | + | * **IEEE754 Multiplication Article** - {{ac-is:teme-ie:c0383011016.pdf| Implementation and Simulation of Ieee 754 Single-Precision Floating Point Multiplier}} |
| - | + | * **Booth Multiplication Algorithm** - [[https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm|Wiki]] | |
| - | * Multiplication algorithms - wiki | + | * **Booth Multiplication Another Example** - [[https://www.javatpoint.com/booths-multiplication-algorithm-in-coa|Click]] |
| - | ===== Anexă ===== | + | ===== Appendix ===== |
