• Soft Deadline: 17.01.2026, 23:59
• Hard Deadline: 17.01.2026, 23:59
• Publish date: 07.01.2026
• Last update: 07.01.2026, xx:xx
• History:
  • 07.01.2026, xx:xx
    • Publish the assignment

The primary objective of this assignment is to build up a stronger perspective around the MARIE architecture and to further develop your proficiency in Verilog. You will:

• Use the MARIE simulator to examine the micro-operations associated with each instruction;
• Correlate the observed instruction behavior with its corresponding Verilog implementation;
• Design and implement several new instructions in Verilog, and use the provided test cases to verify and analyze their correct functionality.

For this assignment, you will continue the implementation of the MARIE CPU instruction set architecture (ISA) by adding support for the following instructions:

• Subt X - Subtract value at address X from the AC.
• JnS X - Store the address of the next instruction into memory at address X, then jump to X + 1.
• LoadI X - Use the contents at address X as the address of the value to load into the AC.
• LoadImmi X - Set the AC to the given 12-bit unsigned immediate value X. (This instruction overwrites the Clear instruction)
• SkipCond X - Skip the next instruction if the condition indicated by X holds (see details in the textbook)

The file to be modified is control_unit.v. Several states shall be added for each instruction in order to implement the desired instructions. You can follow the micro-operations suggested in the recourse files. Each micro-operation shall have one individual state.

• The implementation shall be similar to the approach we had during the labs, by developing the state machine in the control_unit.v file;
• The number of the states is not limited; you can implement each instruction separately or make use of the common states that are already implemented.
• Implement each instruction and test it individually; debug is easier this way.

• In the project recourses there are already the files that you need and the prerequisite modules.
• The project archive that you shall upload (zip compression type) must include in it's root only:
  • the project folder, compressed in a zip archive format;
  • a README file, which shall contain at least:
    • your name and group;
    • general presentation of your solution;
    • description of any complex coding parts that you consider additional explanation is needed and they are too long to be an inline comment;

• +10.0 pts.: Correct implementation with the test passing (2.0 pts for each instruction)
• -10.0 pts.: using looping instructions with variable steps (i.e. while x > 0);
• -1.0 pts.: the absence of the README file;
• -1.0 pts.: bad coding style (chaotic indentation, irregular spacing, strange naming for variables, etc.);
• -0.5 pts.: incorrect using of continuous assignments ( assign ), procedural blocking ( = ) and non-blocking ( ⇐ ) assignments;
• -0.2 pts.: other generic implementation issues (/issue);
• -0.1 pts.: useless code comments.

Even if you do not finish the assignment, you can receive up to 25% of the grade if you properly explain your idea in the README file. Your code must pass the compilation and run.

• VIVADO Project Files - skel_vivado
• MARIE Simulator DATABOOK - MARIE Sim Databook
• MARIE Simulator - MARIE Sim