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ac-is:teme-ie:course_project [2026/01/07 17:51] ionut.pascal [Objectives] |
ac-is:teme-ie:course_project [2026/01/17 21:40] (current) ionut.pascal [MARIE - Extend the ISA] |
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| ====== MARIE - Extend the ISA ====== | ====== MARIE - Extend the ISA ====== | ||
| - | * Soft Deadline: **17.01.2026**, **23:59** | + | * Deadline: <del>**17.01.2026**, **23:59**</del> **18.01.2026**, **11:59** |
| - | * Hard Deadline: **17.01.2026**, **23:59** | + | |
| * Publish date: **07.01.2026** | * Publish date: **07.01.2026** | ||
| - | * Last update: **07.01.2026, xx:xx** | + | * Last update: **17.01.2026, 21:35** |
| * History: | * History: | ||
| - | * 07.01.2026, xx:xx | + | * 07.01.2026, 19:05 |
| - | * Publish the assignment | + | * Assignment published, without the code skeleton and associated tests. |
| + | * 14.01.2026, 17:05 | ||
| + | * Update the skeleton and provide sanity tests for each instruction; Add flags port in the ''control_unit.v''; use it for SkipCond | ||
| + | * Update the implementation section with testing istructions | ||
| + | * 17.01.2026, 21:35 | ||
| + | * Typo found in RAM.v for LoadI testcase | ||
| + | * Increase deadline | ||
| + | <note important>**There is no fix provided in skeleton!** Please do a local change as suggested on the forum!</note> | ||
| ===== Objectives ===== | ===== Objectives ===== | ||
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| ===== Description and requirements ===== | ===== Description and requirements ===== | ||
| - | For this assignment you shall continue the implementation of our MARIE CPU ISA with the following instructions: | + | For this assignment, you will continue the implementation of the MARIE CPU instruction set architecture (ISA) by adding support for the following instructions: |
| - | * Input - Request user to input a value (saves the value from the input to the InReg) | + | * Subt X - Subtract value at address X from the AC. |
| - | * Store X - Stores Contents of AC into Address X (RAM[X] <- AC) | + | * JnS X - Store the address of the next instruction into memory at address X, then jump to X + 1. |
| - | * StoreI X - Stores value in AC at the indirect address (RAM[RAM[X]] <- AC) | + | * LoadI X - Use the contents at address X as the address of the value to load into the AC. |
| - | * LoadI X - Loads value from indirect address into AC ( AC <- RAM[RAM[X]] ) | + | * LoadImmi X - Set the AC to the given 12-bit unsigned immediate value X. (This instruction overwrites the Clear instruction) |
| - | * SkipCond C - Skips the next instruction based on C | + | * SkipCond X - Skip the next instruction if the condition indicated by X holds //(see details in the textbook)// |
| - | <note important>You can find the implementation both in Chapter 4 of the book and in the Databook of the simulator!</note> | + | <note important>You can refer to the implementation details in Chapter 4 of the textbook as well as in the simulator’s Databook. Some instructions constitute extensions of the original set of proposed instructions; their descriptions are provided **exclusively** in the Databook. </note> |
| - | ===== Implementation ===== | + | ===== Implementation & Testing===== |
| - | The file to be modified is control_unit.v. Several states shall be added for each instruction in order to implement the desired instructions. You can follow the micro-operations suggested in the recourse files. Each micro-operation shall have one individual state. | + | The file to be modified is ''control_unit.v''. Several distinct states must be introduced for each instruction to achieve the required functionality. The micro-operations outlined in the simulator should be used as a guide. Each micro-operation should be associated with its own separate state. |
| - | <note important>In the simulator you can take the basic example and add your desired instruction. If you assemble and run through micro-step, you can see each instruction executed step-by-step. Your implementation can follow it!</note> | + | <note important>In the simulator, you may begin with a basic example. After assembling and executing the program in micro-step mode, you will be able to observe each instruction being carried out step-by-step. Your implementation may follow it!</note> |
| + | {{ :ac-is:teme-ie:jns.jpg?link&700 | RTN instruction description using the simulator}} | ||
| + | |||
| + | For validation purposes, multiple tests were developed to ensure the correctness of the implementation. Test 0 runs by default and is expected to pass. When implementing a specific instruction, switch to the corresponding ''define''. Each test includes both previously implemented instructions and the instruction under test; therefore, the tasks are independent and have no dependencies on one another. | ||
| + | |||
| + | <code> | ||
| + | `define test_legacy 0 //legacy test for all the lab implemented instructions | ||
| + | `define test_subst 1 //simple test for Subst | ||
| + | `define test_jns 2 //simp test for JNS | ||
| + | `define test_loadI 3 //simp test for LoadI | ||
| + | `define test_loadImmi 4 //simp test for LoadImmi | ||
| + | `define test_skipCond 5 //simp test for SkipCond | ||
| + | | ||
| + | parameter test_scenario = `test_legacy; //Change the desired test here | ||
| + | </code> | ||
| + | |||
| + | After the test completes, the first indication of your implementation’s correctness is in the log message (see the images below). If the test passes, great job ^_^ ! If the test fails, debug it step by step by analyzing the waveform and comparing it with the assembly program. The ''.asm'' instructions are available in the ''ram.v'' file; load them into the MARIE simulator and run them for reference. | ||
| + | |||
| + | {{ :ac-is:teme-ie:pass_message.jpg?nolink&700 | Pass Messaage}} | ||
| + | |||
| + | {{ :ac-is:teme-ie:fail_message.jpg?nolink&700 | Fail Messaage}} | ||
| ===== Notes ===== | ===== Notes ===== | ||
| - | * The implementation shall be similar to the approach we had during the labs, by developing the state machine in the control_unit.v file; | + | * Your project must include a **README** file describing the details of your implementation, including the state machine implemented in the ''control_unit''. Inline comments within the Verilog code are also encouraged. |
| - | * The number of the states is not limited; you can implement each instruction separately or make use of the common states that are already implemented. | + | * The implementation should follow the methodology used during the laboratory sessions. |
| - | * Implement each instruction and test it **individually**; debug is easier this way. | + | * There is no restriction on the number of states; you may implement each instruction separately or reuse the common states that have already been implemented. |
| + | * Each instruction should be implemented and tested individually, as this approach simplifies debugging. A separate test-case is provided for this case. | ||
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| * a README file, which shall contain at least: | * a README file, which shall contain at least: | ||
| * your name and group; | * your name and group; | ||
| - | * general presentation of your solution; | + | * general presentation of your solution and the FSM diagram (it can be handwritten with a picture attached); |
| * description of any complex coding parts that you consider additional explanation is needed and they are too long to be an inline comment; | * description of any complex coding parts that you consider additional explanation is needed and they are too long to be an inline comment; | ||
| | | ||
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| ===== Grading ===== | ===== Grading ===== | ||
| - | * +10.0 pts.: Correct implementation with the test passing (2.0 pts for each instruction) | + | * +10.0 pts.: correct implementation with the test passing (2.0 pts for each instruction) |
| + | * -10.0 pts.: compilation failed; | ||
| * -10.0 pts.: using looping instructions with variable steps (i.e. while x > 0); | * -10.0 pts.: using looping instructions with variable steps (i.e. while x > 0); | ||
| - | * -1.0 pts.: the absence of the README file; | + | * -50% pts.: the absence of the README file; |
| + | * -2.0 pts.: the files are not correctly uploaded in the moodle section; | ||
| * -1.0 pts.: bad coding style (chaotic indentation, irregular spacing, strange naming for variables, etc.); | * -1.0 pts.: bad coding style (chaotic indentation, irregular spacing, strange naming for variables, etc.); | ||
| - | * -0.5 pts.: incorrect using of continuous assignments ( assign ), procedural blocking ( = ) and non-blocking ( <= ) assignments; | + | * -1.0 pts.: incorrect using of continuous assignments ( assign ), procedural blocking ( = ) and non-blocking ( <= ) assignments; |
| * -0.2 pts.: other generic implementation issues (/issue); | * -0.2 pts.: other generic implementation issues (/issue); | ||
| - | * -0.1 pts.: useless code comments. | + | * -0.1 pts.: useless code comments; |
| + | * +0.5 pts.: bonus for original implementation. | ||
| - | Even if you do not finish the assignment, you can receive up to 25% of the grade if you properly explain your idea in the README file. Your code must pass the compilation and run. | + | Even if the test(s) are not passing, each instruction may account for up to 25% of it's associated points if you clearly explain he underlying approach in the README file. The submitted code **must compile successfully**. |
| + | The final score will be scaled in the Grade section according to the weighting defined at the beginning of the course. | ||
| ===== Recourses ===== | ===== Recourses ===== | ||
| - | * **VIVADO Project Files** - {{:ac-is:teme-ie:MARIEproject_vivado.zip| skel_vivado}} | ||
| - | * **MARIE Simulator DATABOOK** - [[https://marie.js.org/book.pdf|MARIE Sim Databook]] | ||
| * **MARIE Simulator** - [[https://marie.js.org |MARIE Sim ]] | * **MARIE Simulator** - [[https://marie.js.org |MARIE Sim ]] | ||
| + | * **VIVADO Project Files** - {{:ac-is:teme-ie:proj_skel.zip| skel_vivado}} | ||
| + | |||
| + | <ifauth @ac-is> | ||
| + | </ifauth> | ||
| ===== Appendix ===== | ===== Appendix ===== | ||
