In order to implement the exercises, use the lab archive below, considering the simulator you have on your workstation. The files already have a Xilinx ISE / Vivado project that you are able to run; the checking will be performed visually during the lab practice. Follow the instructions and hints below and the zones marked with TODO in the corresponding files.

1. Starting from the interface of sequential_multiplier, inplement a finite state machine that use the module register with different sizes. The implementation shall follow the next rules:
   • When the write signal is high, write each register (A and B) with the proper inputs;
   • When the execute signal is high, the values from the input registers are extracted (read), execute the operation and save (write) the result in the corresponding register
   • When the display signal high, put the values at the output of the module (read the result)
   • The priorities are in order write-execute-display i.e. if write and execute are 1 in the same time, the execute signal is ignored and the module enters WRITE stage
   • Hint: Study the connections between the modules.
   • Hint: Write and read can be controlled through we and oe; go again through lab2 exercises.
   • Hint: Writing the state diagram on paper always helps!

1. (6p) Sequential ALU
   1. (3p) Add the operation input to the module op and modify the scenario in order to exercise this new feature
   2. (3p) Explain the given test scenario and answer the questions
2. Pedestrian Semaphore

• XILINX lab files
• VIVADO lab files
• XILINX home assignment files
• VIVADO home assignment files