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ac-is:lab-ie:lab03 [2023/11/24 19:27] ionut.pascal |
ac-is:lab-ie:lab03 [2023/11/24 20:15] (current) ionut.pascal [Lab practice] |
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| - Starting from the interface of **sequential_multiplier**, inplement a finite state machine that use the module **register** with different sizes. The implementation shall follow the next rules: | - Starting from the interface of **sequential_multiplier**, inplement a finite state machine that use the module **register** with different sizes. The implementation shall follow the next rules: | ||
| * When the ''write'' signal is high, write each register (A and B) with the proper inputs; | * When the ''write'' signal is high, write each register (A and B) with the proper inputs; | ||
| - | * When the ''execute'' signal is high, the values from the input registers are extracted (read), execute the operation and save (write) the result in the corresponding register | + | * When the ''execute'' signal is high, the values from the input registers are extracted (read), execute the operation and save (write) the result in the corresponding register; |
| - | * When the ''display'' signal high, put the values at the output of the module (read the result) | + | * When the ''display'' signal high, put the values at the output of the module (read the result); |
| - | * The priorities are in order ''write-execute-display'' i.e. if ''write'' and ''execute'' are 1 in the same time, the ''execute'' signal is ignored and the module enters WRITE stage | + | * The priorities are in order ''write-execute-display'' i.e. if ''write'' and ''execute'' are 1 in the same time, the ''execute'' signal is ignored and the module enters WRITE stage. |
| * //Hint//: Study the connections between the modules. | * //Hint//: Study the connections between the modules. | ||
| * //Hint//: Write and read can be controlled through ''we'' and ''oe''; go again through lab2 exercises. | * //Hint//: Write and read can be controlled through ''we'' and ''oe''; go again through lab2 exercises. | ||
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| * //Hint//: There are two steps of the implementation: instantate and connect the modules between them in the //trecere.v// file and implement the functionality in //trecere_fsm.v// | * //Hint//: There are two steps of the implementation: instantate and connect the modules between them in the //trecere.v// file and implement the functionality in //trecere_fsm.v// | ||
| * //Hint//: Analyse the counter.v implementation. It resembles the counter implemented in lab2, however it is not the same. You must use it in your implementation. | * //Hint//: Analyse the counter.v implementation. It resembles the counter implemented in lab2, however it is not the same. You must use it in your implementation. | ||
| - | | + | * //Hint//: Search for ToDo's inside |
| + | {{:ac-is:lab-ie:trecere_iec.png?700|}} | ||
| + | |||
| + | {{:ac-is:lab-ie:semaphore_iec.png?700|}} | ||
| ===== Resources ===== | ===== Resources ===== | ||
| * {{ac-is:lab-ie:lab3_xilinx.zip|XILINX lab files}} | * {{ac-is:lab-ie:lab3_xilinx.zip|XILINX lab files}} | ||
