In order to implement the exercises, use the lab archive below, considering the simulator you have on your workstation. The files already have a Xilinx ISE / Vivado project that you are able to run; in addition, for this practice you already have a testing module; the checking will be performed visually during the lab practice. Follow the instructions and hints below and the zones marked with TODO in the corresponding files.

1. Implement an 8bit Adder, with 2 inputs and one output.
   1. The implementation shall contain only continuous assignments;
      • Hint: Before starting the implementation take a minute to analyze the demo-exercise which was done during the introduction. The project can be found below.
   2. The implementation shall use a procedural block;
      • Hint: Don't forget to consult the basics of Verilog from Lab0 until you are familiarized with the new programming language.
      • Hint: Follow the proper tutorial for understanding the simulation; skip the test-adding part if needed.
   3. Add extra stimuli in order to have the carry bit exercised.
      • Hint: The values must be added in the adder8_test, the file which drives the stimuli to our module.
2. Implement a 4bit Comparator using a using a procedural block. This module has 2 inputs and 3 outputs ( less than, equal, grater than).
   • Note: In procedural blocks, the outputs shall have a value at any moment so that they do not become memory components at the synthesis level. Considering this, it is useful to initialize them in the beginning.
   • Optional: You can try implementing it using the only continuous assignment; '?' operator can be handful.
3. Implement a 4:1 Multiplexer. Try to explain the generated waveform.
   1. The implementation shall include a case construction.
      • Hint: Do not forget about the default state!
   2. Let's make this tricky. Implement the multiplexor using the ' ? ' operator.
      • Note: The ' ? ' operator can replace case or if-elseif-else statements when using the assign. However, abusing it can lead to a not-so-understandable implementation.

1. Change the adder8 module from exercise 1 by including a carry bit as an additional input. You can use any of a or b implementation. Add at least 5 data sets in adder8_test.sv, which should exercise the module by assigning differnent values to the inputs.
   • Hint: You should modify the interface and the logic inside.
   • Hint: Think about the corner cases.
   • Note: A complete testing shall exercise all of the inputs.
2. Implement a 8bit multiplier, with 2 inputs and one output.
   • Hint: Take as reference the adder8 module.
   • Hint: What is the size of the output? Consider the highest 8bit number.
3. Implement a tiny ALU (Arithmetical Logical Unit), that shall be able to execute 16bit ADD and SUB operations. The ALU has 3 inputs, op1 (16bits), op2(16bits), sel(1bit) and 2 outputs, result(16bits) and carry(1bit).
   • Hint: Sel input selects the operation that is executed: 0 - ADD, 1 - SUB
   • Hint: You can use the concatenate operator { } in order to make the result a 17bit variable!
   • Note: When you operate the ALU inside a CPU, you have a fixed length bus available for all the data.

• XILINX work files
• VIVADO work files
• XILINX home assignment files
• VIVADO home assignment files