In order to implement the exercises, use the lab archive below, considering the simulator you have on your workstation. The files already have a Xilinx ISE / Vivado project that you are able to run; in addition, for this practice you already have a testing module; the checking will be performed visually during the lab practice. Follow the instructions and hints below and the zones marked with TODO in the corresponding files.

1. Implement an 8bit Adder, with 2 inputs and one output.
   1. The implementation shall contain only continuous assignments;
   2. The implementation shall use a procedural block;
      • Hint: Don't forget to consult the basics of Verilog from Lab0 until you are familiarized with the new programming language.
      • Hint: Follow the proper tutorial for understanding the simulation; skip the test-adding part if needed.
   3. Add extra stimuli in order to have the carry bit exercised.
      • Hint: Values must be added in the adder8_test, the file which drives the stimuli to our module.
2. Implement a 4bit Comparator using only continuous assignments. This module has 2 inputs and 3 outputs ( less than, equal, grater than).
   • Hint: To verify a condition, '?' operator can be used.
3. Implement a 4:1 Multiplexer. Try to explain the generated waveform.
   1. The implementation shall include a case construction.
      • Hint: Do not forget about the default state!
   2. Let's make this tricky. Implement the multiplexor using the ' ? ' operator.
      • Note: The ' ? ' operator can replace case or if-elseif-else statements when using the assign. However, abusing it can lead to a not-so-understandable implementation

Work in progress…

1. (2p) Change the adder
2. (4p) Construct a multiplier
3. (3p) Change the comparator - implement using if statements
4. (4p) Mini - ALU

• XILINX work files
• VIVADO work files