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ac-is:lab-ie:lab01 [2023/11/07 21:42] ionut.pascal [Home assignment] |
ac-is:lab-ie:lab01 [2025/10/28 15:40] (current) ionut.pascal [Home practice] |
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| - Implement an 8bit **Adder**, with 2 inputs and one output. | - Implement an 8bit **Adder**, with 2 inputs and one output. | ||
| - The implementation shall contain only continuous assignments; | - The implementation shall contain only continuous assignments; | ||
| + | * //Hint//: Before starting the implementation take a minute to analyze the demo-exercise which was done during the introduction. The project can be found below. | ||
| - The implementation shall use a procedural block; | - The implementation shall use a procedural block; | ||
| * //Hint//: Don't forget to consult the basics of Verilog from Lab0 until you are familiarized with the new programming language. | * //Hint//: Don't forget to consult the basics of Verilog from Lab0 until you are familiarized with the new programming language. | ||
| Line 13: | Line 14: | ||
| - Add extra stimuli in order to have the carry bit exercised. | - Add extra stimuli in order to have the carry bit exercised. | ||
| * //Hint//: The values must be added in the //adder8_test//, the file which drives the stimuli to our module. | * //Hint//: The values must be added in the //adder8_test//, the file which drives the stimuli to our module. | ||
| - | - Implement a 4bit **Comparator** using only continuous assignments. This module has 2 inputs and 3 outputs ( less than, equal, grater than). | + | - Implement a 4bit **Comparator** using a using a procedural block. This module has 2 inputs and 3 outputs ( less than, equal, grater than). |
| - | * //Hint//: To verify a condition, '**?**' operator can be used. | + | * //Note//: In procedural blocks, the outputs shall have a value at any moment so that they do not become memory components at the synthesis level. Considering this, it is useful to **initialize them in the beginning**. |
| + | * //Optional//: You can try implementing it using the only continuous assignment; '**?**' operator can be handful. | ||
| - Implement a 4:1 **Multiplexer**. Try to explain the generated waveform. | - Implement a 4:1 **Multiplexer**. Try to explain the generated waveform. | ||
| - The implementation shall include a case construction. | - The implementation shall include a case construction. | ||
| * //Hint//: Do not forget about the //default// state! | * //Hint//: Do not forget about the //default// state! | ||
| - Let's make this tricky. Implement the multiplexor using the ' **?** ' operator. | - Let's make this tricky. Implement the multiplexor using the ' **?** ' operator. | ||
| - | * //Note//: The ' **?** ' operator can replace //case// or //if-elseif-else// statements when using the **assign**. However, abusing it can lead to a not-so-understandable implementation | + | * //Note//: The ' **?** ' operator can replace //case// or //if-elseif-else// statements when using the **assign**. However, abusing it can lead to a not-so-understandable implementation. |
| - | ==== Home assignment ==== | + | ==== Home practice ==== |
| - | For the home assignment, you should use the corresponding resources from below. | + | |
| - | - **(2p)** Change the adder8 module from exercise 1 by including a carry bit as an additional input. You can use any of //a// or //b// implementation. Add at least 5 data sets in adder8_test.sv, which will exercise the module and upload a screenshot with the simulation waveform to emphasize them. | + | - Change the //adder8// module from exercise 1 by including a carry bit as an additional input. You can use any of //a// or //b// implementation. Add at least 5 data sets in adder8_test.sv, which should exercise the module by assigning differnent values to the inputs. |
| * //Hint//: You should modify the interface and the logic inside. | * //Hint//: You should modify the interface and the logic inside. | ||
| - | * //Hint//: A complete testing shall exercise all of the inputs. | + | * //Hint//: Think about the corner cases. |
| - | - **(4p)** Implement a 8bit multiplier, with 2 inputs and one output. | + | * //**Note**//: A complete testing shall exercise all of the inputs. |
| + | * **For enthusiasts**: Try the implementation using [[https://www.researchgate.net/publication/283037309/figure/fig2/AS:454461651984390@1485363509931/Eight-bit-Ripple-Carry-adder.png|Ripple Carry Adder]]. | ||
| + | - Implement an //8bit multiplier//, with 2 inputs and one output. | ||
| * //Hint//: Take as reference the adder8 module. | * //Hint//: Take as reference the adder8 module. | ||
| * //Hint//: What is the size of the output? Consider the highest 8bit number. | * //Hint//: What is the size of the output? Consider the highest 8bit number. | ||
| - | - **(3p)** Change the implementation of the comparator, following the rules below: | + | - Implement a tiny ALU (**A**rithmetical **L**ogical **U**nit), that shall be able to execute 16bit ADD and SUB operations. The ALU has 3 inputs, op1 (16bits), op2(16bits), sel(1bit) and 2 outputs, result(16bits) and carry(1bit). |
| - | * Implement it using if constructs, using a procedural block; | + | * //Hint//: Sel input selects the operation that is executed: 0 - ADD, 1 - SUB |
| - | * Change the size of the inputs to 6 bits. | + | |
| - | * //Hint//: Do not forget to use the reg type when needed! | + | |
| - | - **(4p)** Implement a tiny ALU (**A**rithmetical **L**ogical **U**nit), that shall be able to execute 16bit ADD and SUB operations. The ALU has 2 inputs, op1 (16bits) and op2(16bits) and 2 outputs, result(16bits) and carry(1bit). | + | |
| * //Hint//: You can use the concatenate operator { } in order to make the result a 17bit variable! | * //Hint//: You can use the concatenate operator { } in order to make the result a 17bit variable! | ||
| * //Note//: When you operate the ALU inside a CPU, you have a fixed length bus available for all the data. | * //Note//: When you operate the ALU inside a CPU, you have a fixed length bus available for all the data. | ||
| ===== Resources ===== | ===== Resources ===== | ||
| - | * {{ac-is:lab-ie:lab1_xilinx.zip|XILINX work files}} | + | |
| - | * {{ac-is:lab-ie:lab1_vivado.zip|VIVADO work files}} | + | * {{ac-is:lab-ie:lab1_demo.zip|Demo exercise files}} |
| - | * {{ac-is:lab-ie:lab1ha_xilinx.zip|XILINX home assignment files}} | + | * {{ac-is:lab-ie:lab1_vivado_2025.zip|Lab practice files}} |
| - | * {{ac-is:lab-ie:lab1ha_vivado.zip|VIVADO home assignment files}} | + | * {{ac-is:lab-ie:lab1ha_vivado.zip|Home practice files}} |
| <ifauth @ac-is> | <ifauth @ac-is> | ||
| ---- | ---- | ||
| + | * {{ac-is:lab-ie:lab1_xilinx.zip|XILINX work files}} | ||
| + | * {{ac-is:lab-ie:lab1ha_xilinx.zip|XILINX home assignment files}} | ||
| * {{.:lab01:sol:lab1_sol.zip|Soluție laborator}} | * {{.:lab01:sol:lab1_sol.zip|Soluție laborator}} | ||
| * [[ac-is:internal:guidelines|Ghid asistent]] | * [[ac-is:internal:guidelines|Ghid asistent]] | ||
| </ifauth> | </ifauth> | ||
