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ep:labs:03:contents:tasks:ex5 [2026/01/14 14:00] radu.mantu |
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| ==== 05. [10p] Bonus - Hardware Counters ==== | ==== 05. [10p] Bonus - Hardware Counters ==== | ||
| - | |||
| - | <note> | ||
| - | Solve the rest of the lab within the allotted time to unlock this bonus exercise ;) | ||
| - | </note> | ||
| A significant portion of the system statistics that can be generated involve hardware counters. As the name implies, these are special registers that count the number of occurrences of specific events in the CPU. These counters are implemented through **Model Specific Registers** (MSR), control registers used by developers for debugging, tracing, monitoring, etc. Since these registers may be subject to changes from one iteration of a microarchitecture to the next, we will need to consult chapters 18 and 19 from [[https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.html|Intel 64 and IA-32 Architectures Developer's Manual: Vol. 3B]]. | A significant portion of the system statistics that can be generated involve hardware counters. As the name implies, these are special registers that count the number of occurrences of specific events in the CPU. These counters are implemented through **Model Specific Registers** (MSR), control registers used by developers for debugging, tracing, monitoring, etc. Since these registers may be subject to changes from one iteration of a microarchitecture to the next, we will need to consult chapters 18 and 19 from [[https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.html|Intel 64 and IA-32 Architectures Developer's Manual: Vol. 3B]]. | ||
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| Under normal circumstances, modifying Control Registers from userspace is not possible and you would have to write a kernel module for this. However, the [[https://man.archlinux.org/man/perf_event_open.2#perf_event_related_configuration_files|perf_event_open() man page]] documents a //sysfs// interface (i.e., ''/sys/bus/event_source/devices/cpu/rdpmc'') that does this for us. | Under normal circumstances, modifying Control Registers from userspace is not possible and you would have to write a kernel module for this. However, the [[https://man.archlinux.org/man/perf_event_open.2#perf_event_related_configuration_files|perf_event_open() man page]] documents a //sysfs// interface (i.e., ''/sys/bus/event_source/devices/cpu/rdpmc'') that does this for us. | ||
| - | Use the //sysfs// interface to revert the **rdpmc** access behavior to the pre-4.0 version. | + | Use the //sysfs// interface to revert the **RDPMC** access behavior to the pre-4.0 version. |
| + | |||
| + | <solution -hidden> | ||
| + | <code bash> | ||
| + | $ echo 2 | sudo tee /sys/bus/event_source/devices/cpu/rdpmc | ||
| + | </code> | ||
| + | </solution> | ||
| === Task C - Configure IA32_PERF_GLOBAL_CTRL === | === Task C - Configure IA32_PERF_GLOBAL_CTRL === | ||
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| An easier alternative to scouring through the Intel manuals would be to use [[https://perfmon-events.intel.com/platforms/tigerlake/core-events/core/|perfmon-events.intel.com]]. Get your CPU //"model name"// from ''/proc/cpuinfo'' and identify your microarchitecture based on the table below. Then search for the desired event in the appropriate section of the site. | An easier alternative to scouring through the Intel manuals would be to use [[https://perfmon-events.intel.com/platforms/tigerlake/core-events/core/|perfmon-events.intel.com]]. Get your CPU //"model name"// from ''/proc/cpuinfo'' and identify your microarchitecture based on the table below. Then search for the desired event in the appropriate section of the site. | ||
| - | ^ Generation ^ Marketing Name ^ Microarchitecture (Core Codename) ^ Release Year ^ Typical CPU Numbers ^ | + | ^ Generation ^ Microarchitecture (Core Codename) ^ Release Year ^ Typical CPU Numbers ^ |
| - | | 1st | 1st Gen Core i3,5,7 | Nehalem / Westmere | 2008–2010 | i3,5,7 3xx–9xx | | + | | 1st | Nehalem / Westmere | 2008–2010 | i3,5,7 3xx–9xx | |
| - | | 2nd | 2nd Gen Core i3,5,7 | Sandy Bridge | 2011 | i3,5,7 2xxx | | + | | 2nd | Sandy Bridge | 2011 | i3,5,7 2xxx | |
| - | | 3rd | 3rd Gen Core i3,5,7 | Ivy Bridge | 2012 | i3,5,7 3xxx | | + | | 3rd | Ivy Bridge | 2012 | i3,5,7 3xxx | |
| - | | 4th | 4th Gen Core i3,5,7 | Haswell | 2013 | i3,5,7 4xxx | | + | | 4th | Haswell | 2013 | i3,5,7 4xxx | |
| - | | 5th | 5th Gen Core i3,5,7 | Broadwell | 2014–2015 | i3,5,7 5xxx | | + | | 5th | Broadwell | 2014–2015 | i3,5,7 5xxx | |
| - | | 6th | 6th Gen Core i3,5,7 | Skylake | 2015 | i3,5,7 6xxx | | + | | 6th | Skylake | 2015 | i3,5,7 6xxx | |
| - | | 7th | 7th Gen Core i3,5,7 | Kaby Lake | 2016–2017 | i3,5,7 7xxx | | + | | 7th | Kaby Lake | 2016–2017 | i3,5,7 7xxx | |
| - | | 8th | 8th Gen Core i3,5,7 | Coffee Lake / Amber Lake / Whiskey Lake | 2017–2018 | i3,5,7 8xxx | | + | | 8th | Coffee Lake / Amber Lake / Whiskey Lake | 2017–2018 | i3,5,7 8xxx | |
| - | | 9th | 9th Gen Core i3,5,7,9 | Coffee Lake Refresh | 2018–2019 | i3,5,7,9 9xxx | | + | | 9th | Coffee Lake Refresh | 2018–2019 | i3,5,7,9 9xxx | |
| - | | 10th | 10th Gen Core i3,5,7,9 | Comet Lake / Ice Lake / Tiger Lake | 2019–2020 | i3,5,7,9 10xxx | | + | | 10th | Comet Lake / Ice Lake / Tiger Lake | 2019–2020 | i3,5,7,9 10xxx | |
| - | | 11th | 11th Gen Core i3,5,7,9 | Rocket Lake / Tiger Lake | 2021 | i3,5,7,9 11xxx | | + | | 11th | Rocket Lake / Tiger Lake | 2021 | i3,5,7,9 11xxx | |
| - | | 12th | 12th Gen Core i3,5,7,9 | Alder Lake | 2021–2022 | i3,5,7,9 12xxx | | + | | 12th | Alder Lake | 2021–2022 | i3,5,7,9 12xxx | |
| - | | 13th | 13th Gen Core i3,5,7,9 | Raptor Lake | 2022–2023 | i3,5,7,9 13xxx | | + | | 13th | Raptor Lake | 2022–2023 | i3,5,7,9 13xxx | |
| - | | 14th | 14th Gen Core i3,5,7,9 | Raptor Lake Refresh | 2023–2024 | i3,5,7,9 14xxx | | + | | 14th | Raptor Lake Refresh | 2023–2024 | i3,5,7,9 14xxx | |
| - | | — | Core Ultra 5,7,9 (Series 1) | Meteor Lake | 2023–2024 | Core Ultra 5,7,9 1xx | | + | | — | Meteor Lake | 2023–2024 | Core Ultra 5,7,9 1xx | |
| - | | — | Core Ultra 5,7,9 (Series 2) | Arrow Lake / Lunar Lake | 2024–2025 | Core Ultra 5,7,9 2xx | | + | | — | Arrow Lake / Lunar Lake | 2024–2025 | Core Ultra 5,7,9 2xx | |
| </note> | </note> | ||
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| <code C> | <code C> | ||
| /* hardware counter init */ | /* hardware counter init */ | ||
| - | rdpmc(ecx, eax, edx); | + | rdpmc(0, eax, edx); |
| counter = ((uint64_t)eax) | (((uint64_t)edx) << 32); | counter = ((uint64_t)eax) | (((uint64_t)edx) << 32); | ||
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| /* hardware counter delta */ | /* hardware counter delta */ | ||
| - | rdpmc(ecx, eax, edx); | + | rdpmc(0, eax, edx); |
| counter = (((uint64_t)eax) | (((uint64_t)edx) << 32)) - counter; | counter = (((uint64_t)eax) | (((uint64_t)edx) << 32)) - counter; | ||
| </code> | </code> | ||
