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ep:labs:03:contents:tasks:ex4 [2026/03/16 16:52] florin.stancu |
ep:labs:03:contents:tasks:ex4 [2026/03/16 19:48] (current) radu.mantu |
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| - | ==== 04. [10p] Hardware Counters ==== | + | ==== 04. [20p] Hardware Counters ==== |
| A significant portion of the system statistics that can be generated involve hardware counters. As the name implies, these are special registers that count the number of occurrences of specific events in the CPU. These counters are implemented through **Model Specific Registers** (MSR), control registers used by developers for debugging, tracing, monitoring, etc. Since these registers may be subject to changes from one iteration of a microarchitecture to the next, we will need to consult chapters 18 and 19 from [[https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.html|Intel 64 and IA-32 Architectures Developer's Manual: Vol. 3B]]. | A significant portion of the system statistics that can be generated involve hardware counters. As the name implies, these are special registers that count the number of occurrences of specific events in the CPU. These counters are implemented through **Model Specific Registers** (MSR), control registers used by developers for debugging, tracing, monitoring, etc. Since these registers may be subject to changes from one iteration of a microarchitecture to the next, we will need to consult chapters 18 and 19 from [[https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.html|Intel 64 and IA-32 Architectures Developer's Manual: Vol. 3B]]. | ||
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| $ taskset 0x01 ./mat_mul 1024 | $ taskset 0x01 ./mat_mul 1024 | ||
| </code> | </code> | ||
| + | |||
| + | <note important> | ||
| + | Depending on your CPU cache size, a matrix size of 1024 may be insufficient and you won't see any significant difference between the two arrangements. | ||
| + | |||
| + | You can check your cache size by printing the contents of these files: | ||
| + | ''/sys/bus/cpu/devices/cpu0/cache/index*/size''. Indices 0 and 1 typically correspond to the L1 data and L1 instruction caches respectively (you can double check this by reading the ''type'' file instead of ''size''). Indices 2 and 3 correspond to the L2 and L3 caches. | ||
| + | |||
| + | If you run into this problem, either calculate a sufficiently high matrix size value. Or you can just ballpark it. | ||
| + | </note> | ||
| <solution -hidden> | <solution -hidden> | ||
