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ep:labs:03:contents:tasks:ex4 [2019/10/13 18:33] andrei.crividenco [03. [10p] Monitor the system performance] |
ep:labs:03:contents:tasks:ex4 [2025/03/18 00:49] (current) radu.mantu |
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| - | ==== 03. [10p] Monitor the system performance ==== | + | ==== 04. [25p] Microcode analysis ==== |
| - | <note warning> | + | **llvm-mca** is a machine code analyzer that simulates the execution of a sequence of instructions. By leveraging high-level knowledge of the micro-architectural implementation of the CPU, as well as its execution pipeline, this tool is able to determine the execution speed of said instructions in terms of clock cycles. More importantly though, it can highlight possible contentions of two or more instructions over CPU resources or rather, its [[https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Scheduler_Ports_.26_Execution_Units|ports]]. |
| - | High risk of freezing your computer. Show the assistant your progress before starting this exercise! | + | |
| + | Note that **llvm-mca** is not the most reliable tool when predicting the precise runtime of an instruction block (see [[https://dspace.mit.edu/bitstream/handle/1721.1/128755/ithemal-measurement.pdf?sequence=2&isAllowed=y|this paper]] for details). After all, CPUs are not as simple as the good old AVR microcontrollers. While calculating the execution time of an AVR linear program (i.e.: no conditional loops) is as simple as adding up the clock cycles associated to each instruction (from the reference manual), things are never that clear-cut when it comes to CPUs. CPU manufacturers such as Intel often times implement hardware optimizations that are not documented or even publicized. For example, we know that the CPU caches instructions in case a loop is detected. If this is the case, then the instructions are dispatched once again form the buffer, thus avoiding extra instruction fetches. What happens though, if the size of the loop's contents exceeds this buffer size? Obviously, without knowing certain aspects such as this buffer size, not to mention anything about microcode or unknown hardware optimizations, it is impossible to give accurate estimates. | ||
| + | |||
| + | {{ :ep:labs:01:contents:tasks:cpu_exec_unit.png?800 |}} | ||
| + | <html> | ||
| + | <center> | ||
| + | <b>Figure 2:</b> Simplified view of a single Intel Skylake CPU core. Instructions are decoded into μOps and scheduled out-of-order onto the Execution Units. Your CPUs most likely have (many) more EUs. | ||
| + | </center> | ||
| + | </html> | ||
| + | |||
| + | === [5p] Task A - Preparing the input === | ||
| + | |||
| + | As a simple example we will look at ''task_04/csum.c''. This file contains the `csum_16b1c()` function that computes the 16-bit one's complement checksum used in the IP and TCP headers. | ||
| + | |||
| + | Since **llvm-mca** requires assembly code as input, we first need to translate the provided C code. Because the assembly parser it utilizes is the same as **clang**'s, use it to compile the C program but stop after the LLVM generation and optimization stages, when the target-specific assembly code is emitted. | ||
| + | |||
| + | <code bash> | ||
| + | $ clang -S -masm=intel csum.c # output = csum.s | ||
| + | </code> | ||
| + | |||
| + | <note> | ||
| + | Note how in the [[https://llvm.org/docs/CommandGuide/llvm-mca.html|llvm-mca documentation]] it is stated that the ''LLVM-MCA-BEGIN'' and ''LLVM-MCA-END'' markers can be parsed (as assembly comments) in order to restrict the scope of the analysis. | ||
| + | |||
| + | These markers can also be placed in C code (see [[https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html|gcc extended asm]] and [[https://llvm.org/docs/LangRef.html#inline-assembler-expressions|llvm inline asm expressions]]): | ||
| + | <code c> | ||
| + | asm volatile("# LLVM-MCA-BEGIN" ::: "memory"); | ||
| + | </code> | ||
| + | |||
| + | Remember, however, that this approach is not always desirable, for two reasons: | ||
| + | - Even though this is just a comment, the ''volatile'' qualifier can pessimize optimization passes. As a result, the generated code may not correspond to what would normally be emitted. | ||
| + | - Some code structures can not be included in the analysis region. For example, if you want to include the contents of a ''for'' loop, doing so by injecting assembly meta comments in C code will exclude the iterator increment and condition check (which are also executed on every iteration). | ||
| </note> | </note> | ||
| - | === [5p] Generating a script === | + | === [10p] Task B - Analyzing the assembly code === |
| - | * Create a 1GB file of random generated integers ranging from 1 to 10 million. | + | Use **llvm-mca** to inspect its expected throughput and "pressure points" (check out [[https://en.algorithmica.org/hpc/profiling/mca/|this example]]). |
| - | * Write a script/C program to sort the numbers in this file in ascending order. | + | |
| - | === [5p] Monitoring the performance === | + | One important thing to remember is that **llvm-mca** does not simulate the //behavior// of each instruction, but only the time required for it to execute. In other words, if you load an immediate value in a register via ''mov rax, 0x1234'', the analyzer will not care //what// the instruction does (or what the value of ''rax'' even is), but how long it takes the CPU to do it. The implication is quite significant: **llvm-mca** is incapable of analyzing complex sequences of code that contain conditional structures, such as ''for'' loops or function calls. Instead, given the sequence of instructions, it will pass through each of them one by one, ignoring their intended effect: conditional jump instructions will fall through, ''call'' instructions will by passed over not even considering the cost of the associated ''ret'', etc. The closest we can come to analyzing a loop is by reducing the analysis scope via the aforementioned ''LLVM-MCA-*'' markers and controlling the number of simulated iterations from the command line. |
| - | + | ||
| - | * Monitor the system performance using the tools presented in this tutorial. | + | |
| - | Good to know: | + | To solve this issue, you can set the number of iterations from the command line, so its behavior can resemble an actual loop. |
| + | |||
| + | <note> | ||
| + | Read more on the [[https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Scheduler|Skylake instruction scheduler and ports]]. | ||
| + | |||
| + | A very short description of each port's main usage: | ||
| + | * **Port 0,1:** arithmetic instructions | ||
| + | * **Port 2,3:** load operations, AGU (address generation unit) | ||
| + | * **Port 4:** store operations, AGU | ||
| + | * **Port 5:** vector operations | ||
| + | * **Port 6:** integer and branch operations | ||
| + | * **Port 7:** AGU | ||
| + | |||
| + | The the significance of the SKL ports reported by **llvm-mca** can be found in the [[https://github.com/llvm/llvm-project/blob/d9be232191c1c391a0d665e976808b2a12ea98f1/llvm/lib/Target/X86/X86SchedSkylakeClient.td#L32|Skylake machine model config]]. To find out if your CPU belongs to this category, [[https://github.com/llvm/llvm-project/blob/27c5a9bbb01a464bb85624db2d0808f30de7c996/llvm/lib/TargetParser/Host.cpp#L765|RTFS]] and run an ''inxi -Cx''. | ||
| + | |||
| + | </note> | ||
| + | |||
| + | <note tip> | ||
| + | In the default view, look at the number of micro-operations (i.e.: ''#uOps'') associated to each instruction. These are the number of primitive operations that each instruction (from the x86 ISA) is broken into. Fun and irrelevant fact: the hardware implementation of certain instructions can be modified via microcode upgrades. | ||
| + | |||
| + | Anyway, keeping in mind this ''#uOps'' value (for each instruction), we'll notice that the sum of all //resource pressures per port// will equal that value. In other words //resource pressure// means the average number of micro-operations that depend on that resource. | ||
| + | </note> | ||
| + | |||
| + | === [10p] Task C - In-depth examination === | ||
| + | |||
| + | Now that you've got the hang of things, use the ''-bottleneck-analysis'' flag to identify contentious instruction sequences. | ||
| + | |||
| + | Explain the reason to the best of your abilities. For example, the following two instructions display a register dependency because the ''mov'' instruction needs to wait for the ''push'' instruction to update the RSP register. | ||
| + | |||
| + | <code> | ||
| + | 0. push rbp ## REGISTER dependency: rsp | ||
| + | 1. mov rbp, rsp ## REGISTER dependency: rsp | ||
| + | </code> | ||
| + | |||
| + | How would you go about further optimizing this code? | ||
| + | |||
| + | <note> | ||
| + | Also look at the kernel's implementation of a [[https://elixir.bootlin.com/linux/v6.13.7/source/arch/x86/include/asm/checksum_64.h#L45|checksum calculation]] over the variable IP header. | ||
| + | </note> | ||
| - | * Split the file into smaller chunks that would fit in memory (e.g. 200MB). | + | <solution -hidden> |
| - | * Use a classical sort algorithm for sorting these chunks. | + | llvm-mca -bottleneck-analysis -timeline -iterations=10000 -all-stats csum.s |
| - | * Merge the sorted chunks two by two. Read in memory only two numbers at a time (one from each chunk) starting from the beginning, compare the numbers, write the smallest in the merged file, and read the next number from the chunk that had its number written in the merged file. | + | </solution> |
| - | * Repeat the last step until you obtain the original file sorted. | + | |
