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ep:labs:01:contents:tasks:ex4 [2023/11/13 16:47] radu.mantu |
ep:labs:01:contents:tasks:ex4 [2023/11/14 12:51] (current) radu.mantu |
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| - | <b>Figure 2:</b> Simplified view of a single Intel Skylake CPU core. Instructions are decoded into μOps and scheduled out-of-order onto the Execution Units. | + | <b>Figure 2:</b> Simplified view of a single Intel Skylake CPU core. Instructions are decoded into μOps and scheduled out-of-order onto the Execution Units. Your CPUs most likely have (many) more EUs. |
| </center> | </center> | ||
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| * **Port 6:** integer and branch operations | * **Port 6:** integer and branch operations | ||
| * **Port 7:** AGU | * **Port 7:** AGU | ||
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| + | The the significance of the SKL ports reported by **llvm-mca** can be found in the [[https://github.com/llvm/llvm-project/blob/d9be232191c1c391a0d665e976808b2a12ea98f1/llvm/lib/Target/X86/X86SchedSkylakeClient.td#L32|Skylake machine model config]]. To find out if your CPU belongs to this category, [[https://github.com/llvm/llvm-project/blob/27c5a9bbb01a464bb85624db2d0808f30de7c996/llvm/lib/TargetParser/Host.cpp#L765|RTFS]] and run an ''inxi -Cx''. | ||
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| </note> | </note> | ||
