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output wire Output1 , output wire Output2 , output reg [2:0] Status // ieșiri pe 1 bit assign Output1 = ( CurrentState == STATE_1 ) | ( CurrentState == STATE_2 ); assign Output2 = ( CurrentState == STATE_2 ); // ieșiri pe mai multi biți always@ ( * ) begin Status = 3’b000 ; case ( CurrentState ) STATE_2 : begin Status = 3’b010 ; end STATE_3 : begin Status = 3’b011 ; end endcase end