http://ocw.cs.pub.ro/courses/ 2026-04-08T07:18:48+03:00 http://ocw.cs.pub.ro/courses/ http://ocw.cs.pub.ro/courses/lib/tpl/arctic/images/favicon.ico text/html 2026-01-17T21:40:48+03:00 http://ocw.cs.pub.ro/courses/ac-is/teme-ie/course_project?rev=1768678848&do=diff * Deadline: 17.01.2026, 23:59 18.01.2026, 11:59 * Publish date: 07.01.2026 * Last update: 17.01.2026, 21:35 * History: * 07.01.2026, 19:05 * Assignment published, without the code skeleton and associated tests. * 14.01.2026, 17:05 * Update the skeleton and provide sanity tests for each instruction; Add flags port in the control_unit.v; use it for SkipCond * Update the implementation section with testing istructions text/html 2024-01-08T13:04:47+03:00 http://ocw.cs.pub.ro/courses/ac-is/teme-ie/course_project_assembly?rev=1704711887&do=diff * Soft Deadline: 19.01.2024, 23:59 * Hard Deadline: 19.01.2024, 23:59 * Publish date: 07.01.2024 * Last update: 08.01.2024, 12:00 * History: * 07.01.2024, 22:00 * Publish the assignment - detailed Objectives This is a different kind of assignment for students which are interested in using a CPU rather than building its architecture. The main objective of this project is to get familiar with the assembly language using a dedicated ISA, by accommodating the given examples and i… text/html 2024-01-07T18:47:10+03:00 http://ocw.cs.pub.ro/courses/ac-is/teme-ie/proiect?rev=1704646030&do=diff * Soft Deadline: 22.12.2023, 23:59 * Hard Deadline: 28.12.2023, 23:59 * Publish date: 13.12.2023 * Last update: 13.12.2023, 23:50 * History: * 13.12.2023, 23:50 * Publish the assignment Objectives This assignment exercise the basic notions of Verilog by implementing complex sequential circuits. You will: