http://ocw.cs.pub.ro/courses/ 2026-04-07T23:33:13+03:00 http://ocw.cs.pub.ro/courses/ http://ocw.cs.pub.ro/courses/lib/tpl/arctic/images/favicon.ico text/html 2023-11-06T22:41:47+03:00 http://ocw.cs.pub.ro/courses/ac-is/lab-ie/lab00?rev=1699303307&do=diff Verilog În cadrul laboratorului de Arhitectura Calculatoarelor vom studia un limbaj de descriere a hardware-ului (eng. Hardware Description Language - HDL) numit Verilog. Îl vom folosi pe tot parcursul laboratorului pentru a implementa noțiuni legate de arhitectura calculatoarelor. Limbajele de descriere a hardware-ului sunt folosite în industrie pentru proiectarea și implementarea circuitelor digitale. Cele mai folosite limbaje de descriere a hardware-ului sunt Verilog și VHDL. text/html 2025-10-28T15:40:47+03:00 http://ocw.cs.pub.ro/courses/ac-is/lab-ie/lab01?rev=1761658847&do=diff Exercises In order to implement the exercises, use the lab archive below, considering the simulator you have on your workstation. The files already have a Xilinx ISE / Vivado project that you are able to run; in addition, for this practice you already have a testing module; the checking will be performed visually during the lab practice. Follow the instructions and hints below and the zones marked with TODO in the corresponding files. text/html 2023-11-23T13:54:20+03:00 http://ocw.cs.pub.ro/courses/ac-is/lab-ie/lab02?rev=1700740460&do=diff The flip-flop The hardware elements which can store data can be implemented through sequencial circuits called flip-flops. They store the values depending on the input value and the clock cycle; the stored value can be changed only when the clock has reached another positive transition ( the rising edge of the signal, the moment where a signal goes from low to high). There are 4 major flip-flop types: D, T, SR and JK. Our target is the first one, since it is the one we will use later in our imp… text/html 2023-11-24T20:15:23+03:00 http://ocw.cs.pub.ro/courses/ac-is/lab-ie/lab03?rev=1700849723&do=diff Exercises In order to implement the exercises, use the lab archive below, considering the simulator you have on your workstation. The files already have a Xilinx ISE / Vivado project that you are able to run; the checking will be performed visually during the lab practice. Follow the instructions and hints below and the zones marked with TODO in the corresponding files. text/html 2024-12-02T22:00:11+03:00 http://ocw.cs.pub.ro/courses/ac-is/lab-ie/lab04?rev=1733169611&do=diff Intro Fetch Stage Exercises In order to implement the exercises, use the lab archive below, considering the simulator you have on your workstation. The files already have a Xilinx ISE / Vivado project that you are able to run; the checking will be performed visually during the lab practice. Follow the instructions and hints below and the zones marked with TODO in the corresponding files. text/html 2025-12-08T22:34:59+03:00 http://ocw.cs.pub.ro/courses/ac-is/lab-ie/lab05?rev=1765226099&do=diff Load;Store;Add Resources * [VIVADO lab files] text/html 2025-12-15T21:17:33+03:00 http://ocw.cs.pub.ro/courses/ac-is/lab-ie/lab06?rev=1765826253&do=diff Jump / StoreI SkipCond (Bonus; Implement a change in assembly to test it) Resources * [VIVADO lab files] * [MARIE Sim file]