adder4 Project Status
Project File: adder4.xise Parser Errors: No Errors
Module Name: adder4 Implementation State: Translated
Target Device: xc3s500e-4fg320
  • Errors:
X 2 Errors (2 new)
Product Version:ISE 14.7
  • Warnings:
2 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 4 4656 0%
Number of 4 input LUTs 7 9312 0%
Number of bonded IOBs 13 232 5%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed 6. Oct 20:43:43 202101 Warning (1 new)0
Translation ReportCurrentWed 6. Oct 20:43:52 2021X 2 Errors (2 new)1 Warning (0 new)0
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMon 11. Oct 14:38:57 2021

Date Generated: 10/11/2021 - 14:39:06