adder4 Project Status | |||
Project File: | adder4.xise | Parser Errors: | No Errors |
Module Name: | adder4 | Implementation State: | Translated |
Target Device: | xc3s500e-4fg320 |
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X 2 Errors (2 new) |
Product Version: | ISE 14.7 |
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2 Warnings (1 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 4 | 4656 | 0% | |
Number of 4 input LUTs | 7 | 9312 | 0% | |
Number of bonded IOBs | 13 | 232 | 5% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed 6. Oct 20:43:43 2021 | 0 | 1 Warning (1 new) | 0 | |
Translation Report | Current | Wed 6. Oct 20:43:52 2021 | X 2 Errors (2 new) | 1 Warning (0 new) | 0 | |
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Mon 11. Oct 14:38:57 2021 |