`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/06/2023 11:30:17 PM
// Design Name: 
// Module Name: adder8_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module full_adder_test;

	// Inputs
	reg a;
	reg b;
	reg c_in;

	// Outputs
	wire s;
	wire c_out;
    
    
    // Aux
    reg [3:0] i;
	// Instantiate the Unit Under Test (UUT)
	full_adder uut (
		.s(s),
		.c_out(c_out), 
		.a(a), 
		.b(b),
		.c_in(c_in)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;
        c_in = 0;
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		for (i = 0; i < 8; i = i + 1) begin
		  {c_in, b, a } = i;
		  #5;
		end
		
        
	end
      
endmodule