`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 11/06/2023 11:30:17 PM
// Design Name: 
// Module Name: adder8
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
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// Dependencies: 
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module adder8(
    output [8:0] sum,   //result; it includes an extra bit for the carry
    input [7:0] a,      //1st operand
    input [7:0] b       //2nd operand
    );
    
    //TODO: add the implementation of the adder
endmodule
