`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 11/06/2023 11:44:51 PM
// Design Name: 
// Module Name: comp
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module comp(
    output reg lt,      // 1 if a is less than b, else 0
    output reg eq,      // 1 if a is equal to b, else 0
    output reg gt,      // 1 if a is greater than b, else 0
    input wire [3:0] a,
    input wire [3:0] b
    );
    
    always @ (*) begin
        //TODO: implement the functionality
        
    end
endmodule

