Table of Contents

Floating point multiplication automata

Objectives

This assignment exercise the basic notions of Verilog by implementing complex sequential circuits. You will:

Description and requirements

Floating point has a long history in the engineering field and in computer science. The promoter was Leonardo Torres Quevedo back in 1914; nowadays, we use IEEE754 Standard Implementation. Wiki The assignment consists in implementing a floating point multiplication algorithm for 2 numbers with the following format (S_EEEE_MMMMMMM):

The implementation can follow the proposed state machine: Because we encounter a multiplication of fixed point (mantissa), we should implement a dedicated module responsible for this operation. The Booth algorithm is a suitable option which reduces the complexity but keeps a good understanding behind. The size of the operands is dependent on the size of the mantissa.

Requirements:

  1. Implement Booth algorithm in the dedicated file for 2 8bit operands:
    1. Take 2 random 8bit numbers of your choice and demonstrate the algorithm on the paper;
    2. Implement the Verilog code.
  2. Implement the floating point multiplication algorithm:
    1. Take 2 random 12bit numbers of your choice which respects the floating point format and demonstrate the multiplication on the paper;
    2. Implement the Verilog code.

Don't forget to follow the TODO's inside the code and check for the errors and messages in the console! Checking is implemented inside the testcase!

Implementation

In order to implement the requirements, you shall build a finite state machine to divide the operations executed per clock cycle. This automata communicates with additional modules with determined behavior. The detailed implementation for each module is described below.

floating_point_fsm

Finite state machine to be implemented, this module also acts as a top module for the design (the one that have all the additional modules instantiated in it).

This module respects the following interface: 

module floating_point_fsm(
        input         clk,
        input         rst,
        input         en,
        input [11:0]  a,
        input [11:0]  b,
        output reg    done,
        output [11:0] out
    );

The signals' description for this module is:

Modifying the outputs to output reg is allowed for this module.

The module functionality is:

We already have the input (A and B) and output (RES) registers instantiated inside and also an auxiliary register for saving the multiplication result (MUL) with their control signals for writing and reading and the proper connections with the environment, except the ones with the booth_mul.

This module actively used the booth_mul module to perform any multiplication operations needed.

booth_mul

Implements the Booth multiplication algorithm applied on 2 8bit numbers. This module uses combinational logic - the result is available as soon as the inputs change.

This module respects the following interface: 

module booth_mul(
        input [7:0] op1,
        input [7:0] op2,
        output [15:0] result
    );

The signals' description for this module is:

Modifying the outputs to output reg is allowed for this module.

The module functionality is:

Notes

Additional details

This assignment is an individual assignment; using any code from external sources can be considered as plagiarism and can lead to voiding the accumulated points!

Grading

Remember that you have an error counter already implemented in each testcase inside the project files, which tells you exactly when an error is detected. However, do not count on that; the project evaluation is done manually, after analyzing the code and the anti-plagiarism report.

Even if you do not finish the assignment, you can receive up to 25% of the grade if you properly explain your idea in the README file. Your code must pass the compilation and run.

Recourses

Appendix