In order to implement the exercises, use the lab archive below, considering the simulator you have on your workstation. The files already have a Xilinx ISE / Vivado project that you are able to run; the checking will be performed visually during the lab practice. Follow the instructions and hints below and the zones marked with TODO in the corresponding files.

1. Starting from the interface of sequential_multiplier, inplement a finite state machine that use the module register with different sizes. The implementation shall follow the next rules:
   • When the write signal is high, write each register (A and B) with the proper inputs;
   • When the execute signal is high, the values from the input registers are extracted (read), execute the operation and save (write) the result in the corresponding register;
   • When the display signal high, put the values at the output of the module (read the result);
   • The priorities are in order write-execute-display i.e. if write and execute are 1 in the same time, the execute signal is ignored and the module enters WRITE stage.
   • Hint: Study the connections between the modules.
   • Hint: Write and read can be controlled through we and oe; go again through lab2 exercises.
   • Hint: Writing the state diagram on paper always helps!

1. (5p) Modify the Sequential ALU to allow both ADD and SUB operations. To enable this feature, add a new input port - you can call it how you want it, let's say operation - which selects the operation that is performed in the EXECUTE stage. Add the proper stimuli in the _test file to execute both ADD and SUB on the same input values.
   • Hint: Notice the alu module; it has already a operation port inside. The new port shall only be connected.
   • Hint: You can notice the behavior of the state machine by adding some more stimuli sets, to see how your state machine behaves - specially when more than one command is triggered in the same time.
2. (5p) Implement a pedestrian semaphore FSM. For the pedestrians, the timing is: 60 timeunits for the red colour, 30 timeunits for the green colour. Analyse the state machine from the picture below.
   • Hint: There are two steps of the implementation: instantate and connect the modules between them in the trecere.v file and implement the functionality in trecere_fsm.v
   • Hint: Analyse the counter.v implementation. It resembles the counter implemented in lab2, however it is not the same. You must use it in your implementation.
   • Hint: Search for ToDo's inside

• XILINX lab files
• VIVADO lab files
• XILINX home assignment files
• VIVADO home assignment files