module mux4_1(output out, input[3:0] in, input[1:0] sel);
    // implementare multiplexor 4:1
endmodule

module mux8_1(output out, input[7:0] in, input[2:0] sel);
    mux4_1 m1(out30, in[3:0], sel[1:0]);    // instantiere mux4_1
    mux4_1 m2(out47, in[7:4], sel[1:0]);    // alta instantiere mux4_1
    // logica aditionala
    not(n_sel2, sel[2]);
    and(y1, out30, n_sel2);
    and(y2, out47, sel[2]);
    or(out, y1, y2);
endmodule