MARIE - Extend the ISA

MARIE - Extend the ISA

Soft Deadline: 19.01.2024, 23:59
Hard Deadline: 19.01.2024, 23:59
Publish date: 07.01.2024
Last update: 07.01.2024, 20:00
History:
- 07.01.2024, 20:00
  - Publish the assignment - detailed

Objectives

The main purpose of this assignment is to build up a stronger perspective around the MARIE architecture and enhance your Verilog knowledge. You will:

Use the MARIE simulator in order to observe the micro-operations specific for each instruction;
Link the behavior with the Verilog implementation;
Implement in Verilog the new instructions and follow the testcase to determine the correct behavior.

Description and requirements

For this assignment you shall continue the implementation of our MARIE CPU ISA with the following instructions:

Input - Request user to input a value (saves the value from the input to the InReg)
Store X - Stores Contents of AC into Address X (RAM[X] ← AC)
StoreI X - Stores value in AC at the indirect address (RAM[RAM[X]] ← AC)
LoadI X - Loads value from indirect address into AC ( AC ← RAM[RAM[X]] )
SkipCond C - Skips the next instruction based on C

You can find the implementation both in Chapter 4 of the book and in the Databook of the simulator!

Implementation

The file to be modified is control_unit.v. Several states shall be added for each instruction in order to implement the desired instructions. You can follow the micro-operations suggested in the recourse files. Each micro-operation shall have one individual state.

In the simulator you can take the basic example and add your desired instruction. If you assemble and run through micro-step, you can see each instruction executed step-by-step. Your implementation can follow it!

Notes

The implementation shall be similar to the approach we had during the labs, by developing the state machine in the control_unit.v file;
The number of the states is not limited; you can implement each instruction separately or make use of the common states that are already implemented.
Implement each instruction and test it individually; debug is easier this way.

Additional details

In the project recourses there are already the files that you need and the prerequisite modules.
The project archive that you shall upload (zip compression type) must include in it's root only:
- the project folder, compressed in a zip archive format;
- a README file, which shall contain at least:
  - your name and group;
  - general presentation of your solution;
  - description of any complex coding parts that you consider additional explanation is needed and they are too long to be an inline comment;

This assignment is an individual assignment; using any code from external sources can be considered as plagiarism and can lead to voiding the accumulated points!

Grading

+10.0 pts.: Correct implementation with the test passing (2.0 pts for each instruction)
-10.0 pts.: using looping instructions with variable steps (i.e. while x > 0);
-1.0 pts.: the absence of the README file;
-1.0 pts.: bad coding style (chaotic indentation, irregular spacing, strange naming for variables, etc.);
-0.5 pts.: incorrect using of continuous assignments ( assign ), procedural blocking ( = ) and non-blocking ( ⇐ ) assignments;
-0.2 pts.: other generic implementation issues (/issue);
-0.1 pts.: useless code comments.

Even if you do not finish the assignment, you can receive up to 25% of the grade if you properly explain your idea in the README file. Your code must pass the compilation and run.

Recourses

VIVADO Project Files - skel_vivado
XILINX Project Files - skel_xilinx
MARIE Simulator DATABOOK - MARIE Sim Databook
MARIE Simulator - MARIE Sim

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